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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MC145402/D
MC145402
Advance Information
Serial 13-Bit Linear Codec (A/D and D/A)
The MC145402 is a 13-bit linear monotonic digital-to-analog and analog- to-digital converter implemented in a single silicon-gate CMOS IC. Potential applications include analog interface for Digital Signal Processor (DSP) applications, high speed modems, telephone systems, SONAR, Adaptive Differential Pulse Code Modulation (ADPCM) converters, echo cancellers, repeaters, voice synthesizers, and music synthesizers. * * * * * * * * * * 60 dB Signal-to-(Noise Plus Distortion) Ratio Typical On-Chip Precision Voltage Reference Serial Data Ports Two's Complement Coding 5 V Supply Operation Sample Rates from 100 Hz to 16 kHz (Both A/D and D/A), 100 Hz to 21.3 kHz (A/D Only), and 100 Hz to 64 kHz (D/A Only) Input Sample and Hold Provided On-Chip 5 V CMOS Inputs; Outputs Capable of Driving Two LSTTL Loads Available in a 16-Pin DIP Low Power Consumption: 50 mW Typical, 1 mW Power-Down
16 1
L SUFFIX CERAMIC PACKAGE CASE 620
ORDERING INFORMATION
MC145402L Ceramic Package
PIN ASSIGNMENT
VAG Aout Ain PDI CCI MSI TDF VSS 1 2 3 4 5 6 7 8
*
16 15 14 13 12 11 10 9
VDD RDD RCE RDC TDC TDD TDE VDG
BLOCK DIAGRAM
BANDGAP VOLTAGE REFERENCE 15 RDD
2 Aout
SAMPLE AND HOLD
D/A CONVERTER
DATA SELECTOR
RECEIVE LATCH
RECEIVE SHIFT REGISTER
13 RDC 14 RCE
7 Ain 3 SAMPLE AND HOLD COMPARATOR/ OP AMP SUCCESSIVE APPROXIMATION REGISTER TRANSMIT LATCH TRANSMIT SHIFT REGISTER 10 12 11
TDF TDE TDC TDD
SEQUENCE CONTROLLER
6
5
4
16
8
1 VAG
9 VDG
MSI CCI PDI
VDD VSS
This document contains information on a new product. Specifications and information herein are subject to change without notice.
(c) Motorola, Inc. 1995 MOTOROLA
MC145402 1
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS)
Rating DC Supply Voltage Voltage, Any Pin to VSS DC Current Drain per Pin (Excluding VDD, VSS) Operating Temperature Range Storage Temperature Range Symbol VDD - VSS V I TA Tstg Value - 0.5 to 11 - 0.5 to VDD + 0.5 10 - 40 to + 85 - 85 to + 150 Unit V V mA This device contains circuitry to protect the inputs against damage due to high static voltages or electrical fields; however, it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS (Vin or Vout) VDD on analog inputs/outputs and VDG (Vin or Vout) VDD on digital inputs/outputs. Reliability of operation is enhanced if unused digital inputs are tied to an appropriate logic voltage level (e.g., either VDG or VDD) and unused analog Inputs are tied to VAG.
C C
RECOMMENDED OPERATING CONDITIONS
Parameter DC Supply Voltage Power Dissipation, PDI = 1 Power Dissipation, PDI = 0 Conversion Rate Full Cycle A/D and D/A Short Cycle A/D Short Cycle D/A Pins VDD to VSS VDD to VSS VDD to VSS MSI 0 to 70C Min 9.5 -- -- 0.1 0.1 0.1 3.2 16 x fMSI -- -- 25C Typ 10 50 1 -- -- -- -- -- 3.27 9.5 0 to 70C Max 10.5 80 5 16 21.3 64 512 4096 -- -- Unit V mW mW kHz
Conversion Sequence Rate Data Rate Full Scale Analog Levels (Referenced to 600 )
CCI TDC, RDC AI, AO
kHz kHz Vp dBm
DIGITAL ELECTRICAL CHARACTERISTICS (VDD = 5 V, VSS = - 5 V, VAG = VDG = 0 V, TA = 0 to 70C)
Characteristic High Level Input Voltage Low Level Input Voltage Input Current Input Capacitance High Level Output Voltage Low Level Output Voltage TDD TDD Iout = - 20 A Iout = - 1 mA Iout = - 20 A Iout = - 1 mA Symbol VIH VIL Iin Cin VOH VOL Min 3.5 -- -- -- 4.9 4.3 -- -- Max -- 1.5 1.0 10 -- -- 0.1 0.4 Unit V V A pF V V
MC145402 2
MOTOROLA
CODER AND DECODER PERFORMANCE (VDD = 5 V 5%, VSS = - 5 V 5%, VAG = VDG = 0 V,
Coder (A/D) Characteristic Ch ii Resolution Conversion Time Full Cycle A/D and D/A Short Cycle A/D Short Cycle D/A Min 13 62.5 46.9 -- -- - 0.35 - 15 -- -- 3.2 dBm0 0 dBm0 - 10 dBm0 - 20 dBm0 - 30 dBm0 - 40 dBm0 - 50 dBm0 -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- - 75 61 60 57 50 40 30 20 Max 13 10,000 10,000 -- 1 + 0.35 + 15 -- -- -- -- -- -- -- -- -- Min 13 62.5 -- 15.6 -- - 0.35 -- - 20 -- -- -- -- -- -- -- --
0 dBm0 = 1.60 Vrms = 6.30 dBm (600 ), TA = 0 to 70C, MSI = TDE = RCE = 8 kHz, TDC = RDC = 2.048 MHz, CCI = 256 kHz) Decoder (D/A) Typ -- -- -- -- -- -- -- -- - 79 62 60 59 52 42 32 22 Max 13 10,000 -- 10,000 1 + 0.35 -- + 20 -- -- -- -- -- -- -- -- Unit Ui Bits s
Differential Nonlinearity Gain Error Offset Idle Channel Noise, 3 kHz Low-Pass Signal-to-Noise (Referenced to 1.02 kHz through a fMSI/2 Low-Pass Filter)
LSB dB LSB mV dBm0 dB
ANALOG ELECTRICAL CHARACTERISTICS (VDD = 5 V 5%, VSS = - 5 V 5%, VAG = VDG = 0 V,
Characteristic Input Current AC Input Impedance Input Capacitance Output Voltage Range Power Supply Rejection Ratio (100 mV RMS on VDD or VSS, 0 - 50 kHz) Crosstalk, Ain to Aout and RDD to TDD Referenced to 0 dBm0 @ 1.02 kHz Slew Rate Settling Time (Full Scale) Pin AI AI AI AO AO, TDD AO, TDD AO AO Symbol Iin Zin Cin Vout PSRR -- SR tsettle Min -- 0.5 -- - 3.4 -- -- 1.5 --
0 dBm0 = 1.60 Vrms = 6.30 dBm (600 ), TA = 0 to 70C, MSI = TDE = RCE = 8 kHz, TDC = RDC = 2.048 MHz, CCI = 256 kHz) Typ 0.01 -- -- -- 40 - 90 3 8 Max 1 -- 15 3.4 -- - 75 -- -- Unit A M pF V dB dB V/s s
MOTOROLA
MC145402 3
SWITCHING CHARACTERISTICS
(VDD = + 5 V 5%, VSS = - 5 V 5%, VAG = VDG = 0 V, TA = 0 to 70C, CL = 50 pF, See Figure 1) Characteristic Input Rise Time Input Fall Time Output Rise Time Output Fall Time Pulse Width High Pulse Width Low CCI Pulse Width Low MSI Clock Frequency CCI Clock Frequency TDC and RDC Clock Frequency TDC Rising Edge to TDD Data Valid During TDE High TDE Rising Edge to TDD Data Valid During TDC High TDE Rising Edge to TDD Low-Impedance Propagation Delay TDE Falling Edge to TDD High-Impedance Propagation Delay TDE Rising Edge to TDC Falling Edge Setup Time RDC Bit 0 Falling Edge to Last CCI Falling Edge Prior to MSI MSI Rising Edge to CCI Falling Edge Setup Time Last CCI Rising Edge (Prior to MSI) to TDE Rising Edge Last CCI Rising Edge (Prior to MSI) to First TDC Rising Edge First TDC Falling Edge to Last CCI Rising Edge Prior to MSI RCE Rising Edge to RDC Falling Edge Setup Time RDD Valid to RDC Falling Edge Setup Time RDD Hold Time from RDC Falling Edge RCE, RDC, TDC, TDE, CCI, MSI RCE, RDC, TDC, TDE, CCI, MSI TDD TDD RDC, MSI, CCI, TDC, RCE TDE, MSI, TDC, RCE, RDC Symbol tr tf tr tf twH twL twL fMSI fCCI fDC tp1 tp2 tp3 tp4 tsu1 tsu2 tsu3 tsu4 tsu5 tsu6 tsu6' tsu7 tsu8 tsu9 tsu10 th Min -- -- -- -- 100 100 500 0.1 3.2 16 x fMSI -- -- 0 -- 20 100 20 20 100 100 100 0 20 100 60 100 Max 100 100 80 80 -- -- -- 64 512 4.1 150 150 100 40 -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns kHz kHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns
MC145402 4
MOTOROLA
tsu6 TDE tsu6 tsu1 TDC tp1 TDD tp3 twH MSI tsu4 CCI CCI LAST tsu5 CCI LAST twL tp1 tp4 tsu2
tp2
tsu7
RCE tsu8 RDC tsu10 RDD th S B11 B10 B1 tsu9 tsu3 LAST BIT CLOCK B0
Figure 1. AC Timing Diagram
MOTOROLA
MC145402 5
PIN DESCRIPTIONS
VDD Positive Supply (Pin 16) The most positive power supply, typically + 5 V in split power supply configurations, or + 10 V in single supply systems. VSS Negative Supply (Pin 8) The most negative power supply, typically - 5 V in split power supply configurations, or 0 V in single supply systems. VAG Analog Ground (Pin 1) This is the analog signal reference point. This pin is normally tied to 0 V in split supply operation or VDD/2 in single supply systems. VDG Digital Ground (Pin 9) This is the ground reference for all of the digital input and output pins. CMOS compatible logic signals swing from VDG to VDD where VDG can be established anywhere from VDD - 4.75 V to VSS. Aout Analog Output (Pin 2) This is the output of the decoder's sample and hold circuit and is a 100% duty cycle analog output of the last digital word received and decoded by the decoder. Aout is updated approximately 60 ns after the rising edge of the last CCI prior to MSI (see Figure 2). Aout is capable of driving a 10 k, 50 pF load. Ain Analog Input (Pin 3) This is the high-impedance input to the coder. An A/D cycle begins on the first falling edge of CCI following the rising edge of MSI. Ain is sampled approximately 50 ns after the rising edge of CCI prior to the start of the A/D cycle. PDI Power-Down Input (Pin 4) In normal operation this Input should be tied high. A logic low on this input puts the device into a minimum power dissipation mode. During power-down, all functions stop. Two complete MSI conversion cycles are required to establish normal operation after leaving the power-down mode. CCI Convert Clock Input (Pin 5) This input controls the complete conversion sequence during one MSI cycle and must receive a clock which is 32 times the frequency of MSI. The only exception to 32 times the frequency of MSI is during short-cycle operation. See General Modes of Operation section. CCI must be synchronous and approximately rising edge aligned with MSI.
MSI Master Sync Input (Pin 6) This pin determines the conversion rate for both the coder and the decoder. One A/D and D/A conversion takes place during each period of the digital clock applied to this input (except in short-cycle operation, see General Modes of Operation section). MSI must be synchronous and approximately rising edge aligned with CCI. TDC Transmit Data Clock (Pin 12) Digital data from the coder is serially transmitted from TDD on rising TDC edges whenever TDE is a logic high. TDC must be approximately rising edge aligned with TDE. Generally, if TDC is low when TDE rises, the first rising edge of TDC clocks the first data bit. If TDC is high when TDE rises, the first bit will be clocked by TDE and the first rising edge of TDC after TDE rises will clock out the second data bit. TDE Transmit Data Enable (Pin 10) This pin is used to initiate the serial transfer of data from the coder and provides three-state control of the TDD pin. The rising edge of TDE (or TDC if it follows TDE) signals the start of data transfer from the TDD pin. A resulting high logic level on TDE also releases TDD from its high-impedance state. TDE must remain high throughout the data transfer to keep TDD in the low-impedance state and must return to a low state prior to each data transfer. If TDE remains high for more than 16 TDC clocks, the 16 bits of TDD data will be recirculated. (Note: The A/D cycle begins on the first falling edge of CCI after the rising edge of MSI. The internal transmit latch is updated one and one half CCI periods prior to the start of the A/D cycle. A pulse generated by the logical AND of TDE and the first TDC transfers data to the transmit shift register, and this pulse must not occur when the transmit latch is updated. See Figure 2 and see t su6, t su6, and t su7 of Figure 1. TDD Transmit Digital Data (Pin 11) This is the three-state output data pin from the coder and is controlled by the TDE and TDC pins. TDD is in the high- impedance state whenever TDE is a logic low. The first data bit is output from TDD on the rising edge of TDE (or TDC if it follows TDE) and each subsequent bit is output on rising edges of TDC. Two output data formats are available as described in the TDF pin description below. TDF Transmit Data Format (Pin 7) The 13-bit digital output of the coder is available in one of two 16-bit two's complement formats as determined by the state of this pin. A logic 0 at this pin causes the data from TDD to be in a 16-bit sign-extended format as follows: SSSSM ... L where S, M, and L represent the sign, most significant bit, and the least significant bit, respectively. A logic 1 on this pin formats the data as follows: SM ... LSSS (see Figure 3). RDD data is not affected by the state of this pin and if a "digital loopback" is needed (TDD data looped back into RDD), this pin should be high.
MC145402 6
MOTOROLA
RDC Receive Data Clock (Pin 13) Receive digital data is accepted by the decoder on the first 13 falling edges of RDC after an RCE rising edge. RCE Receive Clock Enable (Pin 14) This pin identifies the beginning of a data transfer into the RDD pin of the decoder. The first 13 falling edges of RDC after an RCE rising edge will clock data into the decoder data input, RDD. RCE must return low prior to each data transfer. Since receive data is latched into the receive latch on the last CCI falling edge prior to MSI, data transfers may not span this falling edge of CCI without loss of data. RDD Receive Digital Data (Pin 15) This pin is the data input to the decoder and is controlled by the RDC and RCE pins described above. Two's complement data are loaded in the following sequence: SM ... L where S, M, and L represent the sign, most significant bit, and the least significant bit, respectively. Only the first 13 bits clocked by RDC after RCE rises will be accepted for decoding. Any additional bits will be ignored (see Figure 3).
frequency. Figure 6 shows a circuit that generates this clocking configuration; see Application Circuits section. SIGNAL TO DISTORTION RATIO Figures 4 and 5 show graphs of typical signal to distortion ratios versus signal level for the MC145402. The presented data is referenced to a 1020 Hz input sinusoidal frequency with signal levels referenced to 600 and transmission level point adjusted (e.g., 0 dBm0 at 600 with a TLP of 6.30 dB is 4.53 V peak-to-peak). For comparison, ideal signal to noise ratios for 9-, 10-, 11-, 12-, and 13-bit A/D and D/A converters are also shown. The equation used for an ideal RMS to RMS signal to distortion ratio is: S/D = N x 6 dB + 1.76 dB where N is the number of bits of resolution, 6 dB per bit, and 1.76 = 20log (3/2). (3/2) is approximately the RMS to RMS ratio of a sine wave to white noise. The signal to noise plus distortion ratio is measured through a brickwall low-pass filter set to the Nyquist frequency of the A/D and D/A sample rate. For an 8 kHz sample rate, the low-pass filter is set to block all signals above 4 kHz. APPLICATION CIRCUITS Figure 6 shows a typical circuit for generating the clock frequencies for the MC145402. This circuit uses an MC74HC4040 and a 2.048 MHz crystal to generate the 256 kHz frequency for internal sequencing, 1.024 MHz for the date clocks, and an 8 kHz sample frequency. A 4.096 MHz crystal could be used for a sample rate of 16 kHz. Figure NO TAG shows the MC145402 interfaced to the DSP56000 digital signal processor. The DSP56000 can internally generate the clocks for the MC145402 using the SSI serial interface. SCK provides the sequencing and data clocks (non-gated continuous dock) and SC2 (setup as the Frame Sync Out, FSL = 0) provides the sample rate and data enables for the MC145402. The divide-by-four circuit to generate the CCI clock is recommended for optimum MC145402 performance, and allows the DSP56000 to clock data in and out of the MC145402 quickly, leaving time available for processing by the DSP before another sample is available. SC0 and SC1 could be used to gate the enables to select up to four devices on the SSI bus. TELEPHONE SYSTEM TRANSMISSION LEVEL POINT FOR A LINEAR A/D OR D/A CONVERTER REFERENCED TO MU-LAW COMPANDING Mu-Law companding, as specified by AT&T and CCITT, requires 8159 quantization levels to implement both A/D and D/A conversion schemes. This is to be mirrored about signal ground for the negative part of the wave form. To implement a 13-bit ( 12-bit) linear converter scheme requires 8192 quantization levels mirrored about signal ground. To specify this converter such that it can be used to interface with, or as an alternative to, telephony based Mu- Law applications, the following is an explanation of the gain translation. A 13-bit linear converter scheme has 8192 quantization levels. The goal is to be able to convert between these two encoding schemes with minimal distortion. This dictates setting the LSBs to the same level. For this to be achieved requires the reference voltage of the linear converter to be
GENERAL INFORMATION
GENERAL MODES OF OPERATION The MC145402 has three modes of operation; a "full" cycle mode and two ``short" cycle modes. The full cycle mode allows simultaneous analog-to-digital (A/D) and digital-to- analog (D/A) operation. The short cycle modes allow either A/D only or D/A only operation. Two MSI cycles are required for the MC145402 to detect which operating mode has been selected. See Figure 2 for full versus short cycle clocking. Full Cycle Operation When operating in the full cycle mode, the MC145402 performs a 13-bit A/D conversion followed by a 13-bit D/A con- version. Full cycle operation is selected by using a CCI frequency that is 32 times the frequency of MSI. MSI is the sample rate frequency. Short Cycle Analog-to-Digital Operation If CCI is 24 times the frequency of MSI, short cycle analog-to-digital operation is selected. This allows a 13-bit A/D conversion only. In this mode, the D/A is not operational and any data applied to the RDD input is ignored. Short Cycle Digital-to-Analog Operation Short cycle digital-to-analog operation is selected by using a CCI clock frequency that is eight times the MSI sample rate. During short cycle D/A operation, A/D operation is disabled and digital data read from TDD is not valid. CLOCKING RECOMMENDATIONS For optimum differential nonlinearity performance, all data transitions on TDD and RDD should be limited to the first four CCI cycles following the rising edge of MSI. This may be achieved by setting MSI = TDE = RCE having a duration of 16 data clock cycles, and TDC = RDC 4 x CCI clock
MOTOROLA
MC145402 7
8192/8159 times the reference voltage of the Mu-Law converter. The peak amplitude of a Mu-Law converter is 3.17 dBm0. The peak level of the linear converter will be 8192/8159 times the peak level of the Mu-Law converter, which is 8192/8159 x 3.17 dBm0. However, you cannot multiply a gain factor by a dBm value without using common term units and math (i.e., we must convert this gain factor to a dB equivalent), which is: 20 log10 (8192/8159) = 0.03 dB With the gain factor in dB, we can add it to the Mu-Law peak level: 3.17 dBm0 + 0.03 dB = 3.20 dBm0 Therefore, the linear converter peak level is 3.20 dBm0.
This is another way of saying the 0 dBm0 level for the linear converter is 3.20 dB below the maximum amplitude. To determine the absolute 0 dBm0 level for the linear converter from the peak level, we calculate the peak level in dBm by: 10 log10 3.27 VpK / 2 ) / (600 ) = 9.50 dBm (600 ) 1 mW
and 3.20 dB below this level is the 0 dBm0 absolute amplitude, which is 9.50 dBm - 3.20 dB = 6.30 dBm (600 ) Therefore, the calibration level, or transmission level point (TLP), for this part is 6.30 dBm (600 ), which is 1.6 Vrms based on the reference voltage of 3.27 V.
MC145402 8
MOTOROLA
FULL CYCLE A/D-D/A 1 8 A/D CONVERSION D/A CONVERSION 16 24
32
MOTOROLA
AI SAMPLED AO UPDATED AND TDD DATA TRANSFERRED INTO THE TRANSMIT LATCH A/D CONVERSION A/D CONVERSION AI SAMPLED TDD DATA TRANSFERRED INTO THE TRANSMIT LATCH D/A CONVERSION D/A CONVERSION D/A CONVERSION D/A CONVERSION AO UPDATED RDD DATA LATCHED INTO THE RECEIVE LATCH
CLOCK CYCLE
MSI
CCI
SHORT CYCLE A/D ONLY
RDD DATA LATCHED INTO THE RECEIVE LATCH
MSI
Figure 2. MC145402 Full and Short Cycle Timing
CCI
SHORT CYCLE D/A ONLY
MSI
CCI
MC145402 9
MC145402 10
S S S S b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 S S b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 S S b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 S
TDE
TDC
TDD (TDF = 0)
TDD (TDF = 1)
Figure 3. MC145402 Digital Data Timing
RCE
RDC
RDD
MOTOROLA
80 70 COMPARED TO 9-13 BIT IDEAL A/D; MSI = 8 kHz; MEASURED THROUGH A LOW-PASS FILTER WITH A BANDWIDTH OF f MSI/2
13-BIT 12-BIT 11-BIT 10-BIT 9-BIT
RMS SIGNAL TO RMS (NOISE + DISTORTION) (dB)
60 50 40 30 20 10 0 - 60 - 50 - 40 - 30 - 20 - 10 0
10
INPUT LEVEL (dBm0) (1020 Hz REFERENCED TO 600 )
Figure 4. MC145402 Encoder (A/D) Signal to Noise Plus Distortion Ratio
80 70 COMPARED TO 9-13 BIT IDEAL D/A; MSI = 8 kHz; MEASURED THROUGH A LOW-PASS FILTER WITH A BANDWIDTH OF f MSI/2
13-BIT 12-BIT 11-BIT 10-BIT 9-BIT
RMS SIGNAL TO RMS (NOISE + DISTORTION) (dB)
60 50 40 30 20 10 0 - 60 - 50 - 40 - 30 - 20 - 10 0
10
INPUT LEVEL (dBm0) (1020 Hz REFERENCED TO 600 )
Figure 5. MC145402 Decoder (D/A) Signal to Noise Plus Distortion Ratio
MOTOROLA
MC145402 11
MC145402 12
SERIAL DATA OUT SERIAL DATA IN MC74HC4040 Q1 +5V VCC Q2 RDD RDC RCE 13-BIT D/A Aout 2 ANALOG VOLTAGE OUT Q3 14 Q4 Q5 MC74HCU04 10 CLK Q7 Q8 Q9 20 pF 0V GND Q12 R 11 MC74HCU04 AND MC74HC11 POWER CONNECTIONS VCC, PIN 14 = + 5 V GND, PIN 7 = 0 V +5V 8 Q11 Q10 1/3 MC74HC11 256 kHz 5 6 4 CCI MIS PDI CONTROL 13 8 kHz 4 Q6 +5V 2 7 11 12 10 TDF TDD TDC TDE 16 VDD VSS 8 0.1 F VDG 9 VAG 1 0.1 F 3 13-BIT A/D A in ANALOG VOLTAGE IN 6 13 15 16 1.024 MHz 9 MC145402 +5V -5V 0V
2.048 MHz
15 M
Figure 6. Typical MC145402 Configuration
20 pF
MOTOROLA
+5V
128 fsample +5V 1/2 MC74HC73 D CLK RQ Q J CLK KR Q Q
32 fsample fsample
+5V
1/2 MC74HC74 VCC
VDD 256 kHz PDI CCI TDC MC145402 RDC RCE Aout Vout
DSP56000 SCK
1.024 MHz
Ain
Vin
+5V SC2
D
R
Q Q
J K
R CLK
Q Q 8 kHz
TDE MSI TDF
CLK
1/2 MC74HC74 SRD VSS STD
1/2 MC74HC73
VAG TDD RDD VSS -5V VDG
Figure 7. The MC145402, 13-Bit Linear Codec, Interfaced to a Motorola DSP56000, Digital Signal Processor, SSI Port
MOTOROLA
MC145402 13
PACKAGE DIMENSIONS
L SUFFIX CERAMIC CASE 620-09
-A16 9
-B1 8
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.770 0.240 0.290 -- 0.165 0.015 0.021 0.050 BSC 0.055 0.070 0.100 BSC 0.009 0.011 -- 0.200 0.300 BSC 0 15 0.015 0.035 MILLIMETERS MIN MAX 19.05 19.55 6.10 7.36 -- 4.19 0.39 0.53 1.27 BSC 1.40 1.77 2.54 BSC 0.23 0.27 -- 5.08 7.62 BSC 0 15 0.39 0.88
-TSEATING PLANE
K E F G D 16 PL 0.25 (0.010)
M
N
M J 16 PL 0.25 (0.010)
M
TB
S
TA
S
DIM A B C D E F G J K L M N
MC145402 14
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MC145402 15
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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MC145402 16
*MC145402/D*
MC145402/D MOTOROLA

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